----------------------------------------------------------------------------
-- Author: Ralf Hildebrandt - Ralf-Hildebrandt@gmx.de
-- testbench for the transfer gate
----------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity transfergate_tbench  is

end transfergate_tbench;



architecture behavior of transfergate_tbench is

signal		a,b,c,d			: std_logic;
signal		enable			: std_ulogic;

component transfergate
port(
	wireA,wireB		: inout std_logic;
	enable			: in    std_ulogic	);
end component;

begin


transfergate_i1 : transfergate
port map(
	wireA=>a,
	wireB=>b,
	enable=>enable	);

transfergate_i2 : transfergate
port map(
	wireA=>b,
	wireB=>c,
	enable=>enable	);

transfergate_i3 : transfergate
port map(
	wireA=>c,
	wireB=>d,
	enable=>enable	);


process
begin
a<='Z';
b<='Z';
c<='Z';
d<='1';
wait;
end process;

process
begin
enable<='0';
wait for 1 us;
enable<='1';
wait for 1 us;
assert false report "Simulation finished!" severity error;
end process;


end behavior;